The present invention relates to increasing data transfer rates in a system that divides data transmission units of different sizes into segments of a fixed size. More particularly, the invention relates to a method for enhancing the write capability of a data traffic management system.
In the field of data communications, data traffic management has become an increasingly important issue. Data traffic management is at the core of maintaining an effective data communications system. A data traffic management system manages the arrival and departure of data transmission units by buffering data transmission units. It should be noted that the term data transmission unit (DTU) will be used in a generic sense throughout this document to mean units which include transmitted data. Thus, such units may take the form of packets, cells, frames, or any other unit as long as data is encapsulated within the unit. Thus, the term DTU is applicable to any and all packets and frames that implement specific protocols, standards or transmission schemes.
As the rate of arrival of data traffic increases, the data traffic management system ensures that all DTUs are received and stored in a buffer memory if they are not immediately transmitted. Without proper data traffic management, DTUs may be lost and, as a result, entire streams of data communication may be compromised. To prevent this, the data traffic management system is included a processor and buffer memory to receive and store incoming data traffic that cannot be immediately transmitted. If there is a large influx of DTUs, a large buffer memory may be necessary to store incoming DTUs efficiently until they can be processed for routing to their destinations.
Data traffic management must also address other data traffic issues caused by the different sizes of incoming DTUs. Most network elements, such as switches and routers, require that these DTUs of different size be divided into fixed size segments. The data traffic management system must therefore measure the size of each incoming DTU and divide the DTU into fixed size segments based on that measurement. Using fixed size segments, these network elements are able to process each segment in a shorter processing cycle. Inefficiencies occur due to the fixed processing speeds of the system processor and the limited amount of data transfer per unit time between the processor and the buffer memory. The processing speeds of the system processor and the amount of data transferred between the processor and the buffer memory cannot be easily increased. For data traffic management systems, the time used by the processor to process the segments may already be in the order of 10-40 ns. Decreasing this processing time for each segment may therefore be difficult.
The amount of buffer memory is crucial for buffering additional DTUs when there are higher influx rates of data traffic. For a high speed line, the data traffic management system may maintain a pool of fixed size buffer structures. These buffer structures are used when, upon arrival of data at the input side of the data traffic management system, DTUs of different size are divided into fixed size segments and stored in a buffer structure. The buffer is structured such that it is divided into a number of fixed size memory locations. Each memory location is capable of storing a fixed size segment. Therefore, the buffer can be filled to capacity or at least more efficiently utilized. If the time required to store each fixed length segment is decreased then the processing time required to store a given DTU is correspondingly decreased. This is due to the fact that each DTU is made up of multiple fixed size segments. Thus, if the time required to store each segment decreases then the total time required to store each DTU decreases. Shorter processing times translate into an improvement in the overall speed of the data traffic management system, as many systems are capable of processing many segments in parallel.
Ideally, each DTU produces a whole number of segments of a predetermined fixed size. In cases where a DTU does not produce a whole number of segments, an additional, under-utilized but fixed size segment is needed. Since the input processor only writes one fixed size segment at a time, the processor is required to devote an entire processing cycle to buffer an underutilized fixed size segment in buffer memory. Such inefficiencies may lead to the data traffic management system being unable to meet data traffic demands at the output side of the data traffic management system. One remedy to this problem is to increase the amount of data being transferred between the processor and the buffer memory.
The present invention seeks to provide a data traffic management system which increases the amount of data transfer per unit of time of DTUs of different sizes into the buffer memory.
The present invention is a method of increasing the amount of data transferred per unit of time to a buffer memory for each write operation in a data traffic management system. The present invention seeks to provide a data traffic management system that has the capability of writing data to the buffer memory at twice its normal rate. The data traffic management system uses a pointer structure that can reference either a single or a dual segment memory bank. A dual segment memory bank enhances the write capability of the data traffic management system by allowing two segments to be simultaneously written to both segment memory banks, with one segment being written to each bank. A pointer data structure with a single/dual indicator (S/D indicator) is used for referencing the memory banks. If the S/D indicator has a D entry, then a dual segment memory bank is addressed. The S/D indicator will have an S entry if a single segment memory bank is addressed. Based on the contents of the S/D indicator, either a single fixed size data segment is written to a single memory bank or two fixed size data segments are written to a dual segment memory bank. The use of dual segment memory banks referenced by a single pointer doubles the write capability of the input processor, as two fixed size segments may be written simultaneously to a dual segment memory bank. The end result is that the processing speed of the input processor of the data traffic management system remains the same while the amount of data capable of being written to the buffer per processing cycle has been doubled. The input processor will still process one DTU at a time but it can now buffer two segments per processing cycle.
This method reduces the overflow of DTUs at the input side of the data traffic management system if the data traffic management system is unable to handle the influx of different size DTUs. The present invention is ideally suited for switch cores where DTUs of different sizes arrive at a high influx rate.
In a first aspect, the present invention provides a system for processing incoming data transmission units of different size, the system including:
a) a first memory means having at least one set of two parallel banks;
b) a second memory means containing a plurality of pointers, each pointer being able to simultaneously reference two parallel memory locations in the at least one set of two parallel memory banks, each of the two parallel memory banks in a set having parallel memory locations referenced by each pointer;
c) processing means for receiving an incoming data transmission unit and dividing the incoming data transmission unit into at least two fixed size segments and writing the at least two fixed size segments in the first memory means; and
d) controlling means for updating each index pointer that points to a pointer in the second memory means and sending the index pointer to the processing means, the pointer being one of the plurality of pointers.
In a second aspect, the present invention provides a system for processing incoming data transmission units of different size, the system including:
a) a first memory means having at least one set of two parallel banks;
b) a second memory means containing a plurality of pointers, each pointer being able to simultaneously reference two parallel memory locations in the at least one set of two parallel memory banks, each of the two parallel memory banks in a set having parallel memory locations referenced by each pointer;
c) processing means for receiving an incoming data transmission unit and dividing the incoming data transmission unit into at least two fixed size segments and writing the at least two fixed size segments in the first memory means; and
d) controlling means for updating each index pointer that points to a pointer in the second memory means and sending the index pointer to the processing means, the pointer being one of the plurality of pointers.
In a third aspect, the present invention provides a method of processing a data transmission unit of different size, the method including the steps of:
a) determining a size of the data transmission unit;
b) if the size of the data transmission unit is greater than a predetermined fixed size of a segment, executing the following steps:
b1) dividing the data transmission unit into at least two portions, each portion having a maximum size equal to the predetermined fixed size of a segment;
b2) retrieving at least one and at most two portions from the data transmission unit;
b3) if one portion is retrieved from step b2), executing the following steps:
b3-1) sending a signal to controlling means, the signal indicating that one portion has been retrieved;
b3-2) retrieving a write index from controlling means to processing means, the write index containing a memory address;
b3-3) assigning the memory address to the one portion retrieved in step b2);
b3-4) assigning a pointer to reference the memory location using the memory address assigned in step b3-3);
b3-5) setting a field indicator in the pointer to indicate that one portion is being referenced;
b3-6) storing the one portion in a memory location of a first memory bank, the memory location having the memory address assigned in step b4-3);
b3-7) storing the pointer in pointer memory;
b4) if two portions are retrieved from step b2), executing the following steps:
b4-1) sending a signal to controlling means, the signal indicating that two portions have been retrieved;
b4-2) retrieving a write index from controlling means to processing means, the write index containing a memory address common to a first memory bank and a second memory bank;
b4-3) assigning the memory address to the two portions;
b4-4) assigning a pointer to reference two memory location using the memory address assigned in step b4-3);
b4-5) setting a field indicator in the pointer to indicate that two portions are being referenced, the two portions comprising a first portion and a second portion;
b4-6) storing the first portion in a memory location in the first memory bank and storing the second portion in a memory location in the second memory bank, both memory locations having the memory address assigned in step b4-3);
b4-7) storing the pointer in pointer memory;
b4-8) repeating step b2) to b4), until the data transmission unit has been retrieved, and assigning the pointer to reference a pointer assigned to the at least one and at most two portions to be retrieved.
In a fourth aspect, the present invention provides a method of processing a request for retrieving a data transmission unit from memory, the method including the steps of:
a) sending a signal to controlling means, the signal indicating that a data transmission unit has been requested;
b) retrieving a pointer index from controlling means to processing means;
c) reading a pointer from pointer memory corresponding to the pointer index retrieved in step b);
d) determining whether one or two portions are referenced by the pointer;
e) determining whether the pointer references an immediately succeeding pointer in pointer memory;
f) if one portion is referenced, executing the following steps:
f1) identifying a memory location referenced by the pointer using a memory address contained in the pointer;
f2) retrieving a first portion from the memory location in a first memory bank;
g) if two portions are referenced, executing the following steps:
g1) identifying two memory locations referenced by the pointer using a memory address contained in the pointer;
g2) retrieving a first portion from a first memory location in a first memory bank and retrieving a second portion from a second memory location in a second memory bank, both memory locations identified in step g1);
g3) incrementing the pointer index;
g4) if the pointer references the immediately succeeding pointer determined in step e), repeating step c) to g).